The High-Speed Serial Interface (HSSI) Processor (HIP) provides a single HSSI, EIA/TIA-612/613 network interface for transmitting and receiving data at rates of up to 52 Mbps. The HIP supports both 16- and 32-bit cyclic redundancy checks (CRCs).HSSI, which was recently standardized as EIA/TIA-612/613, provides access to services at T3 (45 Mbps), E3 (34 Mbps), and Synchronous Optical Network (SONET) STS-1 (51.82 Mbps) rates. The actual rate of the interface depends on the external data service unit (DSU) and the type of service to which it is connected.