Cisco Systems`s channelized digital signal level 3 (DS#) interface processor model 50 is an enhancement to the existing CT3IP-40 for Cisco 7500 and 7000/Route Switch Processor (RSP) series routers. Built on the new VIP2-50 platform, the CT3IP-50 extends the performance and IOS service support of the CT3IP-XX family to greater levels. The CT3IP-50 allows 28 T1 connections to be terminated on a router via a single DS3 connection.The CT3IP-50 functions very much like an M13 multiplexer with each T1 line terminating with or originating into or from an HDLC controller on the port adapter. The CT3IP-50 offers 28 individual T1 channels (bundled in the T3) for serial transmission of data. Each of the T1 channels uses a portion of the T1 bandwidth (fractional T1) or the entire T1 bandwidth for data transmission. Usable bandwidths for each T1 are n x 56 kbps or n x 64 kbps, where n is a number from 1 to 24. The unused portion of the T1 bandwidth, when not running at full T1 speeds, cannot be used and is filled with idle channel data. The T3 section of the CT3IP-50 supports the maintenance data link channel (c-bit parity) as well as payload and network loopbacks. The T1 section of the CT3IP-50 supports facilities data link (FDL) in extended super frame (ESF) framing, as well as network and payload loopbacks. Bit error rate testing (BERT) is supported on each of the T1 links. The BERT testing is only done over a framed T1 signal. The M13 multiplexer performs M12 multiplexing on 4 four T1 signals. (There are seven M12 multiplexers available on board.)The seven M12 multiplexers pass their data to the M23 multiplexer, which takes the seven tributaries and formats them into a DS3 stream. This transmit stream is passed on to the T3 line interface unit (LIU) for transmission out of the BNC connector into a 75-ohm coaxial line. The first three T1 channels of the channelized T3 can be broken out, under software control, to the three DB-15 connectors on the front of the CT3IP-50 for further demultiplexing via a MultiChannel Interface Processor (MIP). This allows three (the first three) of the 28 T1 streams in the channelized T3 to be a channelized T1 stream. The broken-out T1(s) are sent to a T1 LIU, which transmits the T1(s) at the DSX-1 level. (DSX-1 refers to the cross connection point for DS-1 signals.) When operating in this mode, these ports are not CSU ports. They do not detect loop codes, provide ones-density requirements, or respond to any FDL messages. The receiving end (MIP) must provide the CSU functionality. Under software control, each external T1 port can be disabled or enabled. The CT3IP-50 does not support the aggregation of multiple T1s (called inverse muxing or bonding) for higher bandwidth data rates. CT3IP-50 supports Cisco HDLC, Frame Relay, PPP, and SMDS Data Exchange Interface (DXI) encapsulations over each T1 link. For SMDS only, DXI is sent on the T1 line so it needs to connect to an SMDS switch that has direct DXI input. There is a special DB-15 connector on the CT3IP-50, labeled TEST. This test connector allows you to break out any T1 of the T3 stream, under software control. This functionality allows you to break out any of the 28 T1s within the T3 stream for testing (for example, 24-hour BERT testing as is commonly done by telephone companies before a line is brought into service), or for further channelization via a MIP card.